1. Field of the Invention
The present invention relates to a data transferring apparatus and a data transferring method those employ a ring connection system. More particularly, the present invention relates to a technology to improve a usage efficiency of a ring bus.
2. Description of the Related Art
Conventionally, a bus connection system, a ring connection system, a switch connection system and the like have been well known as a connection system to transfer a data at a high speed among a plurality of processors. Because the ring connection system has a various advantages among these, various related arts have been proposed. For example, Japanese Laid Open Patent Application (JP-A-Heisei, 9-200239) discloses “DATA TRANSFERRING METHOD AND INFORMATION PROCESSING SYSTEM THAT USE RING CONNECTION” (hereafter, referred to as “Prior Art”.
As shown in FIG. 1, the data information processing system disclosed in the prior art is provided with a ring bus 50 and a plurality of nodes (four nodes 0 to 3, in an illustrated example) connected to the ring bus 50. Each node is composed of a plurality of modules such as a processor, a memory controller for controlling and a memory, an input output controller for controlling an input output device (I/O) and a DMA (Direct Memory Access) controller.
In this information processing system, sending and receiving of a data is performed by using the packet that is transferred to one-way on ring bus 50. In FIG. 1, it is assumed that the packet is transferred. The operations of the information processing system will be described below.
At first, a writing operation in which each of the nodes 0 to 3 sends out the packet to the ring bus 50 is described. This information processing system is equipped with an independent selection line (not shown) in order that each node obtains a writing right, namely, a right to send out the packet to the ring bus 50.
Each of the nodes 0 to 3 sets the selection line to request the writing operation. By this operation, an investigation whether or not a slot arrived to a node on an upstream side of a self-node is an empty slot is performed. Each node recognizes the obtainment of the writing right, from a fact that a received signal from the selection line is not set, and generates a packet including write data to be transmitted until the empty slot arrives at the self-node. Then, each node sends out to the ring bus 50 the packet generated when the empty slot arrives at the self-node. The writing operation is completed as mentioned above.
Next, a reading operation in which each of the nodes 0 to 3 receives the packet from the ring bus 50 is described. Each of the nodes 0 to 3 transfers the packet sent from the node on the upstream side to a node on a downstream side in its original state, and at the same time, transiently stores in a buffer (not shown) all the packets sent from the node on the upstream side. A validation check of the packet stored in the buffer, namely, a check whether or not which is a packet for the self-node is performed at a cycle after the packet is transferred to the node on the downstream side. If the validity of the packet is confirmed, the packet is captured from the buffer in inside the node. The above configuration enables a reduction of latency of each node.
If the packet is captured from the buffer in inside the node, it is necessary to invalidate the transferred packet that is identical to the captured packet and exists on the ring bus 50. So, the node that captures the packet invalidates the transferred packet when it arrives at the self-node after a round of the ring bus 50. According to this configuration, since a packet, which goes around the ring bus 50, is captured at any node, the unnecessary packet can be surely invalidated. This invalidation enables the concerned slot on the ring bus 50 to be released. As a result, the concerned slot becomes an empty slot.
The operations of the conventional information processing system having the above-mentioned configuration will be described below with reference to a timing chart shown in FIG. 2. Let us suppose that this information processing system is operated under the following condition (1) to (3). It should be noted that, in FIG. 2, cycles assigned to the nodes 0 to 3 are represented by C0 to C3, respectively. The ring bus 50 is represented by RDATA[x], and valid data on this ring bus RDATA[x] is represent by N0 to N3.
(1) Condition 1: The valid data N0 from the node 2 to the node 0 exists on the ring bus.
(2) Condition 2: The node 0 holds write data to be transferred to the node 1.
(3) Condition 3: The node 1 holds write data to be transferred to the node 3.
In FIG. 2, the node 0 is operated as follows. That is, the node 0 receives the valid data N0 from the ring bus 50 at a node 0 cycle C0 (timing T3), and stores in the buffer, also transfers to the next node 1 at the same time. The node 0 holds the write data to be transferred to the node 1. However, the validation check of the data stored in the buffer is done later. Thus, it is impossible to execute the invalidation and send out the write data at the timing T3. Hence, the node 0 waits until an arrival of a next node 0 cycle C0.
The valid data N0 is send out from the node 2 to the ring bus 50 at a node 2 cycle C2 (timing T1). Thus, this valid data N0 is invalidated at a node 2 cycle C2 (timing T5). As a result, the concerned slot becomes an empty slot at the node 2 cycle C2 (timing T5). Its state is maintained even at a next node 3 cycle C3 (timing T6). The node 0 obtains a writing right since the concerned slot becomes an empty slot at a node 3 cycle C3 (timing T6), and sends out as a valid data N1 to the ring bus 50 at a next node 0 cycle C0 (timing T7). This valid data N1 is invalidated at a next node 0 cycle C0 (timing T11).
The node 1 is operated as described below. That is, as mentioned above, the valid data N0 is invalidated at the node 2 cycle C2 (timing T5). Thus, the node 1 holds the write data to be transferred to the node 3, but it can not obtain the writing right since the valid data N0 remains on the ring bus 50 at a node 0 cycle C0 (timing T3). Hence, it waits until an arrival of a next node 1 cycle C1.
At a next node 1 cycle C1 (timing T8), the node 1 receives the valid data N1 sent out from the node 0 at the timing T7. However, it is only the node 0 that can invalidate the valid data N1. Thus, at the timing T8, it is impossible to carry out the invalidation or send out the write data. So, the node 1 further waits until an arrival of the next node 1 cycle C1.
The valid data N1 is sent out from the node 0 to the ring bus 50 at the node 0 cycle C0 (timing T7). Thus, this is invalidated at the node 0 cycle C0 (timing T11). As a result, the concerned slot becomes an empty slot at the node 0 cycle C0 (timing T11). The node 1 obtains the writing right since the concerned slot becomes the empty slot at the node 0 cycle C0 (timing T11) and sends out as a valid data N3 to the ring bus 50 at a next node 1 cycle C1 (timing T12). The node 3 captures this valid data N3 at a node 3 cycle C3 (timing T14).
In the conventional information processing system, the above-mentioned operations are repeated to transfer the data between the plurality of nodes connected to the ring bus. In the conventional information processing system, 14 clocks are required until the completion of the data transfer under the above-mentioned conditions 1 to 3.
As mentioned above, in the conventional information processing system, the validation check of the received data is executed after the received data is captured within the node. Thus, it is impossible to invalidate the received data and write a new data, simultaneously with the reception of the valid data from the ring bus.
In this case, the received data is invalidated after the one round of the ring bus. Thus, after the capture of the valid data, although the data within the slot is originally unnecessary, it occupies the slot until the invalidation is performed. Also, when the node receives the valid data in such a condition that it holds the data to be transmitted, although the transmission data can be sent out by using the slot which was occupied by the captured valid data, it is held until a data identical to the captured data makes a round of the ring bus. As a result, the use efficiency of the ring bus declines.